Interconnected techniques are used in semiconductor processing to electrically interconnect devices over a semiconductor wafer. Historically, the semiconductor industry has used subtractive etch or lift off techniques as a primary metal-patterning technique. Subtractive techniques typically involve depositing a metal layer over a wafer and subsequently masking and etching metal material from over undesired portions of the wafer. Escalating density, performance, and manufacturing requirements associated with semiconductor wiring have led to changes in interconnection technology. To meet these needs, a technology called dual damascene has been developed. See for example, Kaanta, Damascene: A ULSI Wiring Technology, VMIC Conference, Jun. 11-12, 1991, page 144-152; Licata, Dual Damascene AL wiring for 256M DRAM, VMIC Conference, Jun. 27-29, 1995 pages 596-602; U.S. Pat. Nos. 5,595,937, 5,598,027, 5,635,432, and 5,612,254.
This invention arose out of concerns associated with providing improved semiconductor processing methods and structures. In particular, the invention arose out of concerns associated with providing improved processing methods and structures which utilize and comprise dual damascene interconnection technology.